library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity Logic_LDMDR is
   port(Data_Size: in bit; -- word/byte
        MAR_out,Bus_in: in unsigned(15 downto 0);
        LogicLDMDR_out: out unsigned(15 downto 0));
end Logic_LDMDR;

architecture Code of Logic_LDMDR is
--signal count: integer range 0 to 8:=to_integer(Data_Size);
--constant count: integer range 0 to 8:=to_integer(Data_Size);

begin
--count <= to_integer(Data_Size);
process (Bus_in)
  begin
     
  
   if Data_Size = '1' then
        LogicLDMDR_out <= Bus_in;
   elsif Data_Size = '0' then
       if MAR_out(0) = '0' then    --even byte
           LogicLDMDR_out <= Bus_in and "0000000011111111";
           if Bus_in(7) = '1' then 
               LogicLDMDR_out <= Bus_in or "1111111100000000";
           end if;
       elsif MAR_out(0) = '1' then   --odd byte (high)
           if Bus_in(15) = '1' then 
            LogicLDMDR_out <= ((Bus_in srl 8) or "1111111100000000");   --"11111111" & (Mem_bus srl 8);
           else LogicLDMDR_out <= ((Bus_in srl 8) and "0000000011111111");  -- "00000000" & (Mem_bus srl 8);
           end if;
       end if;      
   end if;
 
  end process;   

end Code;

